1. Field of the Invention
The present invention relates to receiving circuits used for wireless communication utilizing electromagnetic induction. The present invention relates to LSI (semiconductor integrated circuit) chips capable of performing wireless communication utilizing electromagnetic induction. The present invention relates to storage media capable of performing wireless communication utilizing electromagnetic induction.
2. Description of the Related Art
An electronic circuit for performing wireless communication utilizing electromagnetic induction by a combination of a semiconductor element such as an LSI chip and a coil has been proposed (Reference 1). For example, the electronic circuit disclosed in Reference 1 can perform communication between LSI chips or between an electronic device and an LSI chip and is expected to be applied to an LSI layering technology, an IC chip, or the like.
For example, in the case where a plurality of LSI chips are stacked and electrically connected, conventionally, a technique by which LSI chips are connected to each other by a connection method such as wire bonding and a technique by which LSI chips are connected to each other by physical formation of a communication path that penetrates the chips themselves and is called a through hole are known. However, these techniques increase cost because advanced wiring connection steps are needed. Further, there are physical limits for obtaining a layered structure of many layers. In the conventional method, a defect such as poor connection in a connection portion is one of the causes of a decrease in yield or reliability.
However, by electrically connecting stacked LSI chips or adjacent LSI chips to each other through wireless communication, complex wiring connection steps are not needed. Thus, the decrease in yield or reliability caused in the wiring connection steps is suppressed, so that a circuit can be easily made large and highly integrated at low cost.
Such a technique of wireless communication utilizing electromagnetic induction can be applied to a small IC chip, a storage medium such as a flash memory, or the like. By application of this technique to the storage medium or the like, an area can be markedly reduced by elimination of an exposed portion of a contact electrode that has been needed; thus, further reduction in the size of the storage medium is expected. In addition, since the exposed electrode is not needed, the IC chip or the storage medium can be covered with resin or the like and be totally waterproof Further, a slot into which a storage medium is inserted can be eliminated from an electronic device. In the above manner, advantageous effects are expected in various aspects.
Here, the structure and operation of the conventional receiving circuit used for wireless communication utilizing electromagnetic induction are described with reference to FIG. 10 and FIGS. 11A to 11C. FIG. 10 is a circuit diagram illustrating a structure example of part of a transmitting circuit and the conventional receiving circuit.
FIGS. 11A to 11C are examples of timing charts at the time when signals are transmitted and received.
A transmitting circuit 10 includes a coil 11. One terminal of the coil 11 is connected to a ground potential line, and a transmitting signal TXDATA is input from the other terminal of the coil 11. A receiving circuit 20 includes a coil 21, two comparators (a comparator 23a and a comparator 23b), and a latch circuit 25 including NAND circuit elements. One terminal of the coil 21 is connected to a ground potential line, and the other terminal of the coil 21 is connected to an inversion input terminal (hereinafter also referred to as a−terminal (a minus terminal)) of the comparator 23a and a non-inversion input terminal (hereinafter also referred to as a+terminal (a plus terminal)) of the comparator 23b.Reference voltage VH and reference voltage VL are input to a+terminal of the comparator 23a and a−terminal of the comparator 23b, respectively. Voltage which is higher than 0 V and voltage which is lower than 0 V are used as the reference voltage VH and the reference voltage VL, respectively. Output terminals of the comparators 23a and 23b are connected to the latch circuit 25, and a receiving signal RXDATA is output from the latch circuit 25.
Here, in order to clearly show the relative position of the two coils of the transmitting circuit 10 and the receiving circuit 20, black circles are shown at one ends of the coils in FIG. 10. Specifically, in the case where a coupling factor is positive, it is assumed that the direction of current with respect to one end of the coil on a primary side at which the black circle is shown is the same as the direction of current with respect to one end of the coil on a secondary side at which the black circle is shown. Note that in this structure, a coupling factor between the two coils is assumed to be positive.
Next, reception operation is described with reference to FIG. 10 and timing charts in FIGS. 11A to 11C. FIG. 11A illustrates transition of the voltage of the transmitting signal TXDATA over time. FIG. 11B illustrates transition of a potential difference VR generated between both ends of the coil 21 over time. FIG. 11C illustrates transition of the voltage of the receiving signal RXDATA over time. Here, the level of VR is equal to the level of voltage input to the−terminal of the comparator 23a and the +terminal of the comparator 23b under the condition that the direction of the one end of the coil 21 in FIG. 10 at which the black circle is shown is positive.
When the voltage of TXDATA fluctuates between high-level voltage and low-level voltage, the potential difference VR is generated in the coil 21 by an electromagnetic induction phenomenon, so that a pulsed voltage waveform as illustrated in FIG. 11B is obtained. When VR exceeds the upper limit voltage VH input to the comparator 23a, high-level voltage is output as the output voltage RXDATA from the latch circuit 25. In contrast, when VR is below the lower limit voltage VL input to the comparator 23b, RXDATA is inverted and low-level voltage is output. The latch circuit 25 holds the last output voltage until the voltage of TXDATA is changed.
With the structure and the operation method, the receiving circuit 20 receives the transmitting signal TXDATA from the transmitting circuit 10 and can restore the transmitting signal TXDATA as the receiving signal RXDATA.
[Reference]
Reference 1: Japanese Published Patent Application No. 2005-228981